Mnemonics

BIT

Bit Manipulation Group
Expansion:
BIT
Usage:
bit {0-7},{r}

Tests if a bit in a specific position of the byte. If it is a 1 then the (Z)ero flag is reset to zero. If it is a 0 bit then the (Z)ero flag is set to a 1.

The bit order is %76543210 (first zero indexed byte begins at least significant).

Z80.CPU instructions
Instruction Description Opcode
BIT 0, A Test bit at position 0 of the byte held in registry A CBA7
BIT 0, B Test bit at position 0 of the byte held in registry B CB40
BIT 0, C Test bit at position 0 of the byte held in registry C CB41
BIT 0, D Test bit at position 0 of the byte held in registry D CB42
BIT 0, E Test bit at position 0 of the byte held in registry E CB43
BIT 0, H Test bit at position 0 of the byte held in registry H CB44
BIT 0, L Test bit at position 0 of the byte held in registry L CB45
BIT 0, (HL) Test bit at position 0 of the byte held in address HL CB46
BIT 0, (IX+dis) Test bit at position 0 of the byte held in address IX+displacement DDCB {??} 46
BIT 0, (IY+dis) Test bit at position 0 of the byte held in address IY+displacement FDCB {??} 46
Z80.CPU instructions
Instruction Description Opcode
BIT 1, A Test bit at position 1 of the byte held in registry A CB4F
BIT 1, B Test bit at position 1 of the byte held in registry B CB48
BIT 1, C Test bit at position 1 of the byte held in registry C CB49
BIT 1, D Test bit at position 1 of the byte held in registry D CB4A
BIT 1, E Test bit at position 1 of the byte held in registry E CB4B
BIT 1, H Test bit at position 1 of the byte held in registry H CB4C
BIT 1, L Test bit at position 1 of the byte held in registry L CB4D
BIT 1, (HL) Test bit at position 1 of the byte held in address HL CB4E
BIT 1, (IX+dis) Test bit at position 1 of the byte held in address IX+displacement DDCB {??} 4E
BIT 1, (IY+dis) Test bit at position 1 of the byte held in address IY+displacement FDCB {??} 4E
Z80.CPU instructions
Instruction Description Opcode
BIT 2, A Test bit at position 2 of the byte held in registry A CB57
BIT 2, B Test bit at position 2 of the byte held in registry B CB50
BIT 2, C Test bit at position 2 of the byte held in registry C CB51
BIT 2, D Test bit at position 2 of the byte held in registry D CB52
BIT 2, E Test bit at position 2 of the byte held in registry E CB53
BIT 2, H Test bit at position 2 of the byte held in registry H CB54
BIT 2, L Test bit at position 2 of the byte held in registry L CB55
BIT 2, (HL) Test bit at position 2 of the byte held in address HL CB56
BIT 2, (IX+dis) Test bit at position 2 of the byte held in address IX+displacement DDCB {??} 56
BIT 2, (IY+dis) Test bit at position 2 of the byte held in address IY+displacement FDCB {??} 56
Z80.CPU instructions
Instruction Description Opcode
BIT 3, A Test bit at position 3 of the byte held in registry A CB5F
BIT 3, B Test bit at position 3 of the byte held in registry B CB58
BIT 3, C Test bit at position 3 of the byte held in registry C CB59
BIT 3, D Test bit at position 3 of the byte held in registry D CB5A
BIT 3, E Test bit at position 3 of the byte held in registry E CB5B
BIT 3, H Test bit at position 3 of the byte held in registry H CB5C
BIT 3, L Test bit at position 3 of the byte held in registry L CB5D
BIT 3, (HL) Test bit at position 3 of the byte held in address HL CB5E
BIT 3, (IX+dis) Test bit at position 3 of the byte held in address IX+displacement DDCB {??} 5E
BIT 3, (IY+dis) Test bit at position 3 of the byte held in address IY+displacement FDCB {??} 5E
Z80.CPU instructions
Instruction Description Opcode
BIT 4, A Test bit at position 4 of the byte held in registry A CB67
BIT 4, B Test bit at position 4 of the byte held in registry B CB60
BIT 4, C Test bit at position 4 of the byte held in registry C CB61
BIT 4, D Test bit at position 4 of the byte held in registry D CB62
BIT 4, E Test bit at position 4 of the byte held in registry E CB63
BIT 4, H Test bit at position 4 of the byte held in registry H CB64
BIT 4, L Test bit at position 4 of the byte held in registry L CB65
BIT 4, (HL) Test bit at position 4 of the byte held in address HL CB66
BIT 4, (IX+dis) Test bit at position 4 of the byte held in address IX+displacement DDCB {??} 66
BIT 4, (IY+dis) Test bit at position 4 of the byte held in address IY+displacement FDCB {??} 66
Z80.CPU instructions
Instruction Description Opcode
BIT 5, A Test bit at position 5 of the byte held in registry A CB6F
BIT 5, B Test bit at position 5 of the byte held in registry B CB68
BIT 5, C Test bit at position 5 of the byte held in registry C CB69
BIT 5, D Test bit at position 5 of the byte held in registry D CB6A
BIT 5, E Test bit at position 5 of the byte held in registry E CB6B
BIT 5, H Test bit at position 5 of the byte held in registry H CB6C
BIT 5, L Test bit at position 5 of the byte held in registry L CB6D
BIT 5, (HL) Test bit at position 5 of the byte held in address HL CB6E
BIT 5, (IX+dis) Test bit at position 5 of the byte held in address IX+displacement DDCB {??} 6E
BIT 5, (IY+dis) Test bit at position 5 of the byte held in address IY+displacement FDCB {??} 6E
Z80.CPU instructions
Instruction Description Opcode
BIT 6, A Test bit at position 6 of the byte held in registry A CB77
BIT 6, B Test bit at position 6 of the byte held in registry B CB70
BIT 6, C Test bit at position 6 of the byte held in registry C CB71
BIT 6, D Test bit at position 6 of the byte held in registry D CB72
BIT 6, E Test bit at position 6 of the byte held in registry E CB73
BIT 6, H Test bit at position 6 of the byte held in registry H CB74
BIT 6, L Test bit at position 6 of the byte held in registry L CB75
BIT 6, (HL) Test bit at position 6 of the byte held in address HL CB76
BIT 6, (IX+dis) Test bit at position 6 of the byte held in address IX+displacement DDCB {??} 76
BIT 6, (IY+dis) Test bit at position 6 of the byte held in address IY+displacement FDCB {??} 76
Z80.CPU instructions
Instruction Description Opcode
BIT 7, A Test bit at position 7 of the byte held in registry A CB7F
BIT 7, B Test bit at position 7 of the byte held in registry B CB78
BIT 7, C Test bit at position 7 of the byte held in registry C CB79
BIT 7, D Test bit at position 7 of the byte held in registry D CB7A
BIT 7, E Test bit at position 7 of the byte held in registry E CB7B
BIT 7, H Test bit at position 7 of the byte held in registry H CB7C
BIT 7, L Test bit at position 7 of the byte held in registry L CB7D
BIT 7, (HL) Test bit at position 7 of the byte held in address HL CB7E
BIT 7, (IX+dis) Test bit at position 7 of the byte held in address IX+displacement DDCB {??} 7E
BIT 7, (IY+dis) Test bit at position 7 of the byte held in address IY+displacement FDCB {??} 7E

Example

ld a, %10101010 ; load the binary value into reg A bit 3, a ; test bit 3 of register a ; if the bit is 1, then the zero flag is reset/0 ; if the bit is 0, then the zero flag is set/1

See also