SLA
I don't think I've understood this correctly, marked for revision
When using the SLA mnemonic, we add a zero to the rightmost or least significant bit which in turn knocks the most significant bit off on to the carry flag. We can do this multiple times until eventually we zero out all of the bits.
The SLA instruction can provide us with a quick way multiply a value by 2 each time or a means of extracting or verifying bits.
This works opposite to the SRL instruction.
| Binary | (Z)ero | (P)arity | (C)arry |
|---|---|---|---|
| 11001010 | 0 | 0 | 1 |
| 10010100 | 0 | 1 | 1 |
| 01010000 | 0 | 1 | 0 |
| 10100000 | 0 | 1 | 0 |
| 01000000 | 0 | 0 | 1 |
| 10000000 | 0 | 0 | 0 |
| 00000000 | 1 | 1 | 1 |
| 00000000 | 1 | 1 | 0 |
| 00000000 | 1 | 1 | 0 |
| 00000000 | 1 | 1 | 0 |
| Instruction | Description | Opcode |
|---|---|---|
| SLA A | Shift bits in A register | CB27 |
| SLA B | Shift bits in B register | CB20 |
| SLA C | Shift bits in C register | CB21 |
| SLA D | Shift bits in D register | CB22 |
| SLA E | Shift bits in E register | CB23 |
| SLA H | Shift bits in H register | CB24 |
| SLA L | Shift bits in L register | CB25 |
| SLA (HL) | Shift bits at memory address HL register | CB26 |
| SLA (IX+displacement) | Shift bits in (IX + displacement) register | DDCB {??}26 |
| SLA (IY+displacement) | Shift bits in (IY + displacement) register | FDCB {??}26 |