SRL
I don't think I've understood this correctly, marked for revision
When using the SRL mnemonic, we add a zero to the leftmost or most significant bit which in turn knocks the least significant bit off on to the carry flag. We can do this multiple times until eventually we zero out all of the bits.
The SRL instruction can provide us with a quick way to divide a value by a division of 2 each time or a means of extracting or verifying bits.
This works opposite to the SLA instruction.
| Binary | (Z)ero | (P)arity | (C)arry |
|---|---|---|---|
| 11001010 | 1 | 1 | 0 |
| 01100101 | 0 | 1 | 0 |
| 00110010 | 0 | 0 | 1 |
| 00011001 | 0 | 0 | 0 |
| 00001100 | 0 | 1 | 1 |
| 00000110 | 0 | 1 | 0 |
| 00000011 | 0 | 1 | 0 |
| 00000001 | 0 | 0 | 1 |
| 00000000 | 1 | 1 | 1 |
| 00000000 | 1 | 1 | 0 |
| Instruction | Description | Opcode |
|---|---|---|
| SRL A | Shift bits in A register | CB3F |
| SRL B | Shift bits in B register | CB38 |
| SRL C | Shift bits in C register | CB39 |
| SRL D | Shift bits in D register | CB3A |
| SRL E | Shift bits in E register | CB3B |
| SRL H | Shift bits in H register | CB3C |
| SRL L | Shift bits in L register | CB3D |
| SRL (HL) | Shift bits at memory address HL register | CB3E |
| SRL (IX+displacement) | Shift bits in (IX + displacement) register | DDCB {??}3E |
| SRL (IY+displacement) | Shift bits in (IY + displacement) register | FD {??}3E |